Bioinformatics Application of a Scalable Supercomputer-On-Chip Architecture

A high level overview of a supercomputer-on-chip (SCoC) architecture is given which is particularly well suited to common bioinformatic computing tasks. The architecture uses asynchronous bus interfaces to create an application specific integrated circuit design methodology allowing for scaling of SCoCs with very little design effort. Standard processors and standard system buses are employed along with the pre-designed bus interface to allow quick generation of massively parallel SCoCs which can be as large as integrated circuit manufacturing technology will allow. A key aspect of this design methodology is that it is not necessary to expend significant design resources and chip area on the clock tree. An analysis of the Smith-Waterman alignment algorithm running on this architecture shows that the performance penalty due to increased bus latency compared to a fully synchronous architecture is negligible.